This invention relates to reduction projection type alignment system for the alignment of a circuit pattern on a mask (reticle) and a wafer at a high accuracy.
As the structures of the semiconductor integrated circuits have become finer, higher accuracy is demanded for the alignment between the reticle and the wafer upon exposure by a reduction projection type exposure at present. In view of the above, it is considered that a TTL alignment system carried out by way of a reduction projection lens capable of alignment on every chips thereby coping with arrangement errors of chips within a wafer will take a leading position in the feature manufacture of densely integrated circuits.
FIG. 1 shows one example of the TTL alignment system, in which the circuit pattern of mask (reticle) 1 is exposed to one or several units of chips 16 at wafer 3 on wafer stage 4 by way of reduction projection type lens 2. The position for initial reticle setting patterns 15 and 15' are at first detected by reticle alignment optical systems 5 and 5' prior to the exposure and the mask (reticle) 1 is thereby set to the initial position. Then, alignment patterns 14 and 14' near the chip 16 on the wafer 3 are focused by way of the reduction projection lens 2 to alignment patterns (window patterns) 13 and 13' on the mask (reticle) 1, and both of the patterns are detected by a wafer alignment detecting optical system. The wafer alignment detecting optical system comprises mirrors 6 and 6', relay lenses 7 and 7', magnifying lenses 8 and 8', movable slits 9 and 9', photomultipliers 10 and 10', optical fibers 11 and 11' for emitting alignment irradiation light at an identical wave length with the exposure light and the like. The irradiation light from the optical fibers 11 and 11' are irradiated through the half mirrors, relay lenses 7 and 7', mirrors 6 and 6' to the alignment patterns 13 and 13', whereas reflection light therefrom are detected by the photomultipliers 10 and 10' by way of the mirrors 6 and 6', relay lenses 7 and 7', half mirrors, magnifying lenses 8 and 8', mirrors and movable slits 9 and 9'. If the detected wafer alignment patterns 14 and 14' do not agree with the positions for the reticle alignment patterns 13 and 13', the wafer stage 4 carrying the wafer 3 is moved in the direction X or Y in accordance with the direction and the extent of the displacement, by which the positions for the patterns 14 and 14' are aligned with those for the patterns 13 and 13'. After the alignment has thus been completed, the exposure light is irradiated through the exposure system 12 to the mask (reticle) 1. The information concerning the alignment system of this type is disclosed, for example, in U.S. Pat. No. 4,362,389.
By the way, the TTL alignment system involves a problem of the lowering in the alignment accuracy caused by the uneven coating of photoresist on the wafer which has been pointed out so far but not yet solved. The problem has become more serious in recent years as the density of the semiconductor circuits has been increased.